1. Field of the Invention
The present invention relates to a semiconductor device fabrication method.
2. Description of the Related Art
As the micropatterning of transistors on silicon semiconductor substrates advances, fin transistors are beginning to be studied instead of the conventional planar transistors. Note that a fin transistor is described in Jpn. Pat. Appln. KOKAI Publication No. 2002-110963. Since fin portions are very fine, however, their patterns cannot be transferred by the conventional resist patterning. Therefore, a method called pattern transfer is used. This pattern transfer roughly comprises the following processes.
First, a silicon nitride film is formed as a primary mask on a buffer film formed on a silicon substrate. This primary mask is then processed by pattern transfer and anisotropic etching using a resist. A silicon oxide film having a thickness x is formed as a secondary mask on the entire surface, and processed by anisotropic etching. In this process, the pattern of the secondary mask having a very small width x is formed around the primary mask. When the primary mask is removed after that, the pattern of the secondary mask having the very small width x is formed on the silicon substrate. Therefore, a silicon pattern having the very small width x can be formed by etching the buffer film and silicon substrate by using this secondary mask.
In this method, however, not only gate portions requiring fine patterns but also pad portions (extended portions of a source and drain) for connecting interconnections are also given fine patterns. Since no sufficient contact area can be obtained, the contact resistance rises.
Note that Jpn. Pat. Appln. KOKAI Publication No. 2002-280388 discloses a technique by which L & S patterns made of a first insulating film are covered with a second insulating film, side walls of the second insulating film are formed on the side surfaces of a first pattern by etch back, and fine L & S patterns are obtained by using the side walls.
Jpn. Pat. Appln. KOKAI Publication No. 2002-359352 discloses a technique by which a first mask pattern is formed on a substrate, a second mask pattern having holes in predetermined portions of the first mask pattern is formed, and very fine patterns are formed by thinning the first pattern in these holes.
U.S. Pat. No. 6,583,469 discloses a method of forming mask patterns for obtaining a structure which connects a narrow channel portion and wide source/drain portions of a fin FET by a moderate tapered shape.